1. Field of the Invention
This invention relates to a semiconductor device with a multi-layered wiring structure, and more particularly to a semiconductor device having two- or more-layered wiring layers each formed of metal.
2. Description of the Related Art
In a recent LSI circuit (large scale integrated circuit) such as a gate array and a CPU (central processing unit), wirings each formed of two or more layers are used to increase the integration of the circuit. Wirings in the LSI are classified as a power line for supplying electric power to the circuit elements and a signal line for transferring various signals to the circuit elements. As shown in FIG. 1, in a CMOS-LSI (CMOS type integrated circuit) having a CMOS inverter constituted by a P-channel MOSFET 31 and an N-channel MOSFET 32, for example, a wiring shown in a thick solid line is a power line 33. A wiring shown in thick broken line is a signal line 34. A DC voltage is applied to the power line 33. A DC current flows in the power line 33 or a DC pulse current intermittently flows according to ON/OFF operations of the circuit elements in the power line 33. In general, the current in the power line 33 flows only in one direction. In contrast, a pulse current in the signal line 34, particularly in the signal line 34 of the CMOS-LSI, flows in both directions as a charging or discharging current with respect to a capacitive load.
As shown in FIG. 2, in the conventional semiconductor device with multi-layered wiring structure, only aluminum or aluminum alloy is used as a metal of the multi-layered wirings 33 and 34. Therefore, in circuit layout in which such multi-layered wirings should be used, the power line 33 and the signal line 34 are not needed to be distinguished clearly from each other. In the device in FIG. 2, reference numeral 1 denotes a silicon semiconductor substrate; 3, a well region; 4 and 5, P.sup.+ -type diffusion regions; 6 and 7, N.sup.+ -type diffusion regions; 8 and 9, polysilicon layers; and 10, a field oxide film.
In the semiconductor device, a maximum current capable of flowing in the wiring is influenced by abrasion failure which is called "electromigration". The rated value of the maximum current is ordinarily determined by a test upon which a DC current is flowed in the wiring. The rated value is, for example, approx. 1.times.10.sup.5 (A/cm.sup.2). Since a relatively large current flows in the power line, the conventional power line may be formed as wide as possible. However, as the circuit elements are miniaturized in a fine pattern, it becomes difficult to obtain the rated value determined by the DC current needed for the power line. Moreover, in the prior art, since the size of the whole chip is not changed even if the sizes of the internal circuit elements and the wirings are reduced in a fine pattern, more particularly, since the lengths of the wirings are not changed but the power source voltage becomes low together with the miniaturized size of the circuit elements, erroneous operation caused by a voltage drop in the power line occurs as a serious problem.
It is well known in the art that there is a certain correlation between a melting point and an electromigration resistance of the metal. A metal such as tungsten having a high melting point can be used as the wiring material. If the wiring of tungsten is used as the signal line, a delay time for signal transmission due to the electric resistance of the tungsten wiring will not cause any problem, since the length of the signal line per a switching element tends to be shortened as the integrated circuit is miniaturized in a fine pattern. However, if the tungsten wiring is used as the power line, the electric resistance thereof is higher than that of the aluminum by several orders and thus the operation error due to the voltage drop becomes a serious problem. Therefore, it is difficult to use the wiring of the tungsten as the power line.